We are only dealing with, SPARC based workstations, in order to check, just type uname -m command and you should read something like sparc4x where x is blank,c,d,m,u if the system runs Solaris, or sparc for 32 bits SPARC architectures and sparc64 for 64 bits SPARC architectures if it runs Linux. 2.2.x
SPARC stands for Scalable Processor ARChitecture, it derives from research done between 1984-1988 on the RISC architecture at UC Berkeley. It exists 3 versions of this archiecture, SPARC-V7, SPARC-V8 ( 32 bits ) and SPARC-V9 ( 64 bits ). As you are likely to encounter a lot of implementations of the SPARC architecture, I have summarized the main features of theses processors.
This is quite obsolete, it is an implementation of the SPARC-V7 ; its main feature are an Integer unit ( IU ), an external Floating Point Unit ( FPU ), an unified data + instruction 64KB direct associative cache, and an Memory Managment Unit ( MMU ). There is a 4 stage pipeline for the integer instructions ( fetch F, decode D, exec E, update WB ) FPU and IU are synchronized
This is Texas Instrument and Sun's brainchild, it is usualy found at clok rates around 50Mhz featuring up to 1MB L2 cache, it is available both on single and dual processor modules ( SparcStation 10 and SparcStation 20 ). The higher clock frequency I have encountered is 60Mhz.
On a technical point of view this is a SPARC-V8 implementation, it is a superscalar processor, having 2 caches, one for instruction the other one for data.
This is once again Texas Instrument and Sun's brainchild, you can find it in the SparcStation Classic, SparcStation LX, at frequency up to 50Mhz. Its derivative the Micro SPARC II can be found in SparcStation 4, SparcStation 5 at frequencies up to 110Mhz.
On a technical point of view, its main features are a high level of integration, having 2 caches, one for instructions, the other one for data.
It is not possible to had an L2 cache. If wish to learn more about the MicroSPARC processor you can browse Sun's Ultra SPARC ressources.
This processor was introduced by ROSS in 1993, it is usualy found in the SparcStation 10, and SparcStation 20, at frequencies up to 150Mhz ( I have heard of 200Mhz dual processor modules, but Have not witnessed one yet ). It can be found on single or dual processor modules.
On a technical point of view it is an implementation of the SPARC-V8, it is superscalar. It can be found with L2 cache up to 512KB
The Ultra SPARC processor is an extension of the SPARC-V9 architecture, it is a 64 bits processor, it features some video processing instructions. It is found in all the workstation whose name start with Ultra.
The Ultra SPARC II is an improvement of the Ultra SPARC, the Ultra SPARCIII is actually the second generation of Ultra SPARC processors, it was first introduced in the SunBlade 1000 Workstation. If wish to learn more about the UltraSPARC processors you can browse Sun's Ultra SPARC ressources.
You may read the CPU-Design-HOWTO, this HOWTO has a lot of interesting links when it comes to studying the CPUs.
To summarize, the 32 bits workstations are the:
For more information on the SparcStation 5, 10, 20 you can read Sun's documentation online or download it available.
The following model have an 64 bits UltraSPARC architecture ( sun4u ). SunUltra 1, 2, 5, 10, 30, 60, 80 and SunBlade 1000. The SunUltra 2, 60, 80 and SunBlade 1000 are SMP capable, with the Ultra 80 and SunBlade 1000 accepting up to 4 CPU modules, the SunUltra 2 and 60 accepting only 2 CPU modules.
The SunBlade 1000 is the latest one featuring Sun's latest marvel the Ultra III CPU, at a premium price of course. You can have a summary of the UltraWorkstation still in production at Sun's website.
A lot of information has been compiled in the Sun hardware reference that is found on AcesHardware's website, or on SunHelp 's website.
At first, a reference like SM61 or RT-200-D-125/512 seems to be, to say the least, quite cryptic. Actually, understanding theses references is really easy.
Theses CPUs's naming scheme is RT-a00-b-freq/cache where
a is a digit:
1 SparcStation 10.2 SparcStation 20.6 SPARC MP600 ( not exactly a workstation ).b is a letter:
D Dual CPU.Q Quad CPU.S Single CPU.freq The frequency expressed in Megahertz.cache The amount of cache memory expressed in Kilobytes.When theses modules are in a workstations the naming convention is HSxy, for example ywing is a SparcStation 20 HS22, thus it is easier to have a look inside the workstation.
This table is extracted from the FAQABOSS
Name Speed( MHz ) Cache( MB ) Number of SuperSparc
Processors Series
SM20 33 0 1 I
SM30 36 0 1 I
SM40 40 0 1 I
SM41 40 1 1 I
SM50 50 0 1 I
SM51 50 1 1 I
SM512 50 1 2 I
SM51-2 50 2 1 I
SM61 60 1 1 I
SM61-2 60 2 1 I
SM71 75 1 1 II
SM71-2 75 2 1 II
SM81 85 1 1 II
SM81-5 85 2 1 II
Warning: the SM100 is a RT-600-D-40
Cypress manufactured SPARC compliants processors; AFAIK their naming scheme is CYnnn.
As you can see, this is easy to understand.